Digital Calibration Method for High Resolution in Analog/RF Designs

2018-12-13T22:07:31Z (GMT) by Renzhi Liu
Transistor random mismatch continuously poses challenges for analog/RF circuit design for<br>achieving high accuracy and high yield as the process technology advances. Existing statistical<br>element selection (SES) design method can improve transistor matching property, but it falls<br>short of being a general calibration method due to its limited calibration range.<br>In this dissertation, we propose a high resolution digital calibration method, called extended<br>statistical element selection (ESES). As compared to the SES method, the ESES method not only<br>provides wider calibration range, but also it results in higher calibration yield with same<br>calibration resolution target. Two types of ESES based calibration application in analog/RF<br>circuits are also proposed. One is current source calibration and the other is phase/delay<br>calibration.<br>To verify this proposed digital calibration method in circuit implementation, we designed,<br>fabricated and tested a wideband harmonic rejection receiver design. The receiver utilizes ESESbased<br>gain and phase error calibration for improving harmonic rejection ratios. With the high<br>calibration resolution provided by the ESES method, after calibration, we achieved best-in-class<br>harmonic rejection ratios. To extend the application of the proposed method, we further designed<br>a current-steering D/A data converter (CS-DAC). The CS-DAC utilizes ESES-based amplitude<br>and timing error calibration for improving linearity performance. Simulation results showed that<br>we can achieve more than one order of magnitude linearity improvement after performing ESESbased<br>calibration in the CS-DAC.